Network-on-Chip

Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends. Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design. This text comprises 12 chapters and covers: - The evolution of NoC from SoC-its research and developmental challenges - NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces - The router design strategies followed in NoCs - The evaluation mechanism of NoC architectures - The application mapping strategies followed in NoCs - Low-power design techniques specifically followed in NoCs - The signal integrity and reliability issues of NoC - The details of NoC testing strategies reported so far - The problem of synthesizing application-specific NoCs - Reconfigurable NoC design issues - Direction of future research and development in the field of NoC Network-on-Chip: The Next Generation of System-on-Chip Integration covers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems.

Santanu Kundu received his BTech in instrumentation engineering from Vidyasagar University, Medinipur, West Bengal, India, in 2002. He received his MTech in instrumentation and electronics engineering from Jadavpur University, Kolkata, West Bengal, India, in 2006. Immediately after that he joined the electronics and electrical communication engineering department at the Indian Institute of Technology, Kharagpur, West Bengal, India. He received his PhD in 2011. His research interests include network-on-chip architecture design in 2D and 3D environments, performance and cost evaluation, signal integrity in nanometer regime, fault-tolerant schemes, and power-performance-reliability trade-off. He is currently a system-on-chip (SoC) design engineer at LSI India R&D Pvt. Ltd., Bangalore, Karnataka, India. Santanu Chattopadhyay received his BE in computer science and technology from Calcutta University (BE College), Kolkata, West Bengal, in 1990. In 1992 and 1996, he received his MTech in computer and information technology and PhD in computer science and engineering, respectively, both from the Indian Institute of Technology (IIT), Kharagpur, West Bengal, India. He is currently a professor in the electronics and electrical communication engineering department at the IIT, Kharagpur. He has contributed to more than 100 publications in refereed international journals and conferences. He has also coauthored and written several textbooks, and is a member of the editorial board of the journal IET Circuits, Devices and Systems.

Introduction System-on-Chip Integration and Its Challenges SoC to Network-on-Chip: A Paradigm Shift Research Issues in NoC Development Existing NoC Examples Summary References Interconnection Networks in Network-on-Chip Introduction Network Topologies Switching Techniques Routing Strategies Flow Control Protocol Quality-of-Service Support NI Module Summary References Architecture Design of Network-on-Chip Introduction Switching Techniques and Packet Format Asynchronous FIFO Design GALS Style of Communication Wormhole Router Architecture Design VC Router Architecture Design Adaptive Router Architecture Design Summary References Evaluation of Network-on-Chip Architectures Evaluation Methodologies of NoC Traffic Modeling Selection of Channel Width and Flit Size Simulation Results and Analysis of MoT Network with WH Router Impact of FIFO Size and Placement in Energy and Performance of a Network Performance and Cost Comparison of MoT with Other NoC Structures Having WH Router under Self-Similar Traffic Simulation Results and Analysis of MoT Network with Virtual Channel Router Performance and Cost Comparison of MoT with Other NoC Structures Having VC Router Limitations of Tree-Based Topologies Summary References Application Mapping on Network-on-Chip Introduction Mapping Problem ILP Formulation Constructive Heuristics for Application Mapping Constructive Heuristics with Iterative Improvement Mapping Using Discrete PSO Summary References Low-Power Techniques for Network-on-Chip Introduction Standard Low-Power Methods for NoC Routers Standard Low-Power Methods for NoC Links System-Level Power Reduction Summary References Signal Integrity and Reliability of Network-on-Chip Introduction Sources of Faults in NoC Fabric Permanent Fault Controlling Techniques Transient Fault Controlling Techniques Unified Coding Framework Energy and Reliability Trade-Off in Coding Technique Summary References Testing of Network-on- Chip Architectures Introduction Testing Communication Fabric Testing Cores Summary References Application-Specific Network-on-Chip Synthesis Introduction ASNoC Synthesis Problem Literature Survey System-Level Floorplanning Custom Interconnection Topology and Route Generation ASNoC Synthesis with Flexible Router Placement Summary References Reconfigurable Network-on-Chip Design Introduction Literature Review Local Reconfiguration Approach Topology Reconfiguration Link Reconfiguration Summary References Three-Dimensional Integration of Network-on-Chip Introduction 3-D Integration: Pros and Cons Design and Evaluation of 3-D NoC Architecture Summary References Conclusions and Future Trends Conclusions Future Trends Comparison between Alternatives References Index